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CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
Integrated Device Technology, Inc.
IDT723631 IDT723641 IDT723651
FEATURES:
* Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) * Clocked FIFO buffering data from Port A to Port B * Storage capacity: IDT723631 - 512 x 36 IDT723641 - 1024 x 36 IDT723651 - 2048 x 36 * Synchronous read retransmit capability * Mailbox register in each direction * Programmable Almost-Full and Almost-Empty flags * Microprocessor interface control logic * Input-Ready (IR) and Almost-Full (AF) flags synchronized by CLKA * Output-Ready (OR) and Almost-Empty (AE) flags synchronized by CLKB * Low-power 0.8-micron advanced CMOS technology
* Supports clock frequencies up to 67 MHz * Fast access times of 11 ns * Available in 132-pin plastic quad flat package (PQF) or space-saving 120-pin thin quad flat package (TQFP) * Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT723631/723641/723651 is a monolithic highspeed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The 512/1024/2048 x 36 dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
Input Register
Sync Retransmit Logic
RST
Reset Logic
Output Register
W/RA ENA MBA
CSA
Mail 1 Register Port-A Control Logic 512 x 36 1024 x 36 2048 x 36 SRAM
RTM RFM B0 - B35 OR
36
A0 - A35
Write Pointer
Read Pointer
AF
FS0/SD FS1/SEN
IR
Status Flag Logic
AE
10
Flag Offset Registers CLKB Port-B Control Logic
CSB W/RB
ENB MBB
Mail 2 Register
MBF2
3023 drw 01
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1997 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3023/3
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
stored in memory. Communication between each port may take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices may be used in parallel to create wider data paths. Expansion is also possible in word depth. The IDT723631/723641/723651 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent
of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE) flag of the FIFO are twostage synchronized to CLKB. Offset values for the almost-full and almost empty flags of the FIFO can be programmed from port A or through a serial input.
PIN CONFIGURATION
NC NC VCC CLKB ENB
GND MBB NC VCC RFM RTM FS1/SEN FS0/SD GND
MBF2 VCC AE AF
NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
CSA
VCC OR IR
W/RA ENA CLKA GND NC
W/RB CSB
MBF1
GND
RST
MBA
*
NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
*El
3023 drw 02
ectrical pin 1 in center of beveled edge. Pin 1 identifier in corner. PQFP (PQ132-1, order code: PQF) TOP VIEW
Notes: 1. NC - No internal connection 2. Uses Yamaichi socket IC51-1324-828
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (CONTINUED)
GND FS0/SD FS1/SEN RTM RFM VCC NC MBB GND
GND CLKA ENA W/RA
AF AE VCC MBF2
A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
RST
CSB W/RB
ENB CLKB VCC
MBF1
GND
MBA
CSA
IR OR VCC
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND
GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 B10 B11
3023 drw 03
Note: 1. NC - No internal connection
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
TQFP (PN120-1, order code: PF) TOP VIEW
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol A0-A35 Name Port-A Data Almost-Empty Flag I/O Description I/O 36-bit bidirectional data port for side A. Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in the almost-empty register (X). O Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in the FIFO is less than or equal to the value in the almost-full offset register (Y). I/O 36-bit bidirectional data port for side B. I CLKA is a continuous clock that synchronizes all data transfers through port-A and may be aynchronous or coincident to CLKB. IR and AF are synchronous to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or coincident to CLKA. OR and AE are synchro nous to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During a device reset, FS1/SEN and FS0/SD selects the flag offset programming method. Three offset register programming methods are available: automatically load one of two preset values, parallel load from port A, and serial load. When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 18/20/22. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit data and prevents further writes. IR is set LOW during reset and is set HIGH after reset. A HIGH level chooses a mailbox register for a port-A read or write operation. A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output. O
AE AF
B0-B35 CLKA
Almost-Full Flag.
Port-B Data. Port-A Clock
CLKB
Port-B Clock
I
CSA CSB
ENA ENB FS1/SEN, FS0/SD
Port-A Chip Select
I
Port-B Chip Select
I
Port-A Enable Port-B Enable Flag-Offset Select 1/ Serial Enable, Flag Offset 0/ Serial Data
I I I
IR
Input-Ready Flag
O
MBA MBB
Port-A Mailbox Select Port-B Mailbox Select
I I
MBF1
Mail1 Register Flag
O
reset.
MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH by a
3023 tbl 01
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol Name Mail2 Register Flag I/O O Description MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a reset. OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are disabled. Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the reset and goes HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory. When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-toHIGH transition of CLKB to reset the read pointer to the beginning retransmit location and output the first selected retransmit data. To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-toHIGH transitions of CLKB must occur while RST is LOW. The LOW-to-HIGH transition of RST latches the status of FS0 and FS1 for AF and AE offset selection. When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial retransmit point until a LOW-to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO out of retransmit mode. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.
3023 tbl 02
MBF2
OR
Output-Ready Flag
O
RFM
Read From Mark
I
RST
Reset
I
RTM
Retransmit Mode
I
W/RA
Port-A Write/Read Select Port-B Write/Read Select
I
W/RB
I
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(2)
Symbol VCC VI
(2) (2)
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, (VI < 0 or VI > VCC) Output Clamp Current, (VO = < 0 or VO > VCC) Continuous Output Current, (VO = 0 to VCC) Continuous Current Through VCC or GND Operating Free Air Temperature Range Storage Temperature Range
Commercial -0.5 to 7 -0.5 to VCC+0.5 -0.5 to VCC+0.5 20 50 50 400 0 to 70 -65 to 150
Unit V V V mA mA mA mA C C
3023 tbl 03
VO
IIK IOK IOUT ICC TA TSTG
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage HIGH Level Input Voltage LOW-Level Input Voltage HIGH-Level Output Current LOW-Level Output Current Operating Free-air Temperature Min. 4.5 2 - - - 0 Max. Unit 5.5 - 0.8 -4 8 70 V V V mA mA C
3023 tbl 04
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter VOH VOL ILI ILO ICC ICC
(2)
Test Conditions VCC = 4.5V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, IOH = -4 mA IOL = 8 mA VI = VCC or 0 VO = VCC or 0 VI = VCC -0.2 V or 0 One Input at 3.4 V,
Min. 2.4
Typ.(1)
Max. 0.5 5 5 400
Unit V V A A A mA
Other Inputs at VCC or GND
CSA = VIH CSB = VIH CSA = VIL CSB = VIL
All Other Inputs
A0-A35 B0-B35 A0-A35 B0-35
0 0 1 1 1 4 8
CIN COUT
VI = 0, VO = 0,
f = 1 MHz f = 1 MHZ
pF pF
3023 tbl 05
NOTES: 1. All typical values are at VCC = 5 V, TA = 25C. 2. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0 V or VCC.
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT723631L15 IDT723631L20 IDT723631L30 IDT723641L15 IDT723641L20 IDT723641L30 IDT723651L15 IDT723651L20 IDT723651L30 Min. Max. Min. Max. Min. Max. - 15 6 6 5 5 7 6 5 9 5 5 0 0 0 0
(1)
Symbol fS tCLK tCLKH tCLKL tDS tENS1 tENS2 tRMS tRSTS tFSS tSDS tDH tENH1 tENH2 tRMH tRSTH tFSH tSPH
(2) (2) (2) (3) (2) (2)
Parameter Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA or CLKB HIGH Pulse Duration, CLKA or CLKB LOW Setup Time, A0-A35 before CLKA and B0-B35 before CLKB Setup Time, ENA to CLKA; ENB to CLKB Setup Time, CSA, W/RA, and MBA to CLKA; CSB, W/RB, and MBB to CLKB Setup Time, RTM and RFM to CLKB Setup Time, RST LOW before CLKA or CLKB(1) Setup Time, FS0 and FS1 before RST HIGH Setup Time, FS0/SD before CLKA Setup Time, FS1/SEN before CLKA Hold Time, A0-A35 after CLKA and B0-B35 after CLKB Hold Time, ENA after CLKA; ENB after CLKB Hold Time, CSA, W/RA, and MBA after CLKA; CSB, W/RB, and MBB after CLKB Hold Time, RTM and RFM after CLKB Hold Time, RST LOW after CLKA or CLKB Hold Time, FS0 and FS1 after RST HIGH Hold Time, FS0/SD after CLKA Hold Time, FS1/SEN after CLKA Skew Time, between CLKA and CLKB for OR and IR Hold Time, FS1/SEN HIGH after RST HIGH
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3023 tbl 06
66.7 - - - - - - - - - - - - - - - - - - - - - -
- 20 8 8 6 6 7.5 6.5 6 10 6 6 0 0 0 0 6 0 0 0 0 11 16
50 - - - - - - - - - - - - - - - - - - - - - -
- 30 12 12 7 7 8 7 7 11 7 7 0 0 0 0 7 0 0 0 0 13 20
33.4 - - - - - - - - - - - - - - - - - - - - - -
tSENS
5 0 0 0 0 9 12
tSDH
tSENH
tSKEW1
tSKEW2(3) Skew Time, between CLKA and CLKB for AE and AF
NOTES: 1. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 2. Only applies when serial load method is used to program flag offset registers. 3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
IDT723631L15 IDT723631L20 IDT723631L30 IDT723641L15 IDT723641L20 IDT723641L30 IDT723651L15 IDT723651L20 IDT723651L30 Min. Max. Min. Max. Min. Max. - 3 1 1 1 1 0 66.7 11 8 8 8 8 8 - 3 1 1 1 1 0 50 13 10 10 10 10 10 - 3 1 1 1 1 0 33.4 15 12 12 12 12 12
Symbol fS tA tPIR tPOR tPAE tPAF tPMF
Parameter Clock Frequency, CLKA or CLKB Access Time, CLKB to B0-B35 Propagation Delay Time, CLKA to IR Propagation Delay Time, CLKB to OR Propagation Delay Time, CLKB to AE Propagation Delay Time, CLKA to AF Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH Propagation Delay Time, CLKA to B0-B35(1) and CLKB to A0-A35(2) Propagation Delay Time, MBB to B0-B35 Valid Propagation Delay Time, RST LOW to AE LOW and AF HIGH
Unit MHz ns ns ns ns ns ns
tPMR tMDV tRSF tEN
3 3 1 2
13.5 13 15 12
3 3 1 2
15 15 20 13
3 3 1 2
17 17 30 14
ns ns ns ns
Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH to B0-B35 Active Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH or W/RB LOW to B0-B35 at high impedance
tDIS
1
8
1
10
1
11
ns
3023 tbl 07
NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
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IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION RESET The IDT723631/723641/723651 is reset by taking the reset (RST) input LOW for at least four port-A clock (CLKA) and four port-B (CLKB) LOW-to-HIGH transitions. The reset input may switch asynchronously to the clocks. A reset initializes the memory read and write pointers and forces the input-ready (IR) flag LOW, the output-ready (OR) flag LOW, the almost-empty (AE) flag LOW, and the almost-full (AF) flag HIGH. Resetting the device also forces the mailbox flags (MBF1, MBF2) HIGH. After a FIFO is reset, its input-ready flag is set HIGH after at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory. ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING Two registers in the IDT723631/723641/723651 are used to hold the offset values for the almost-empty and almost full flags. The almost-empty (AE) flag offset register is labeled X, and the almost-full (AF) flag offset register is labeled Y. The offset register can be loaded with a value in three ways: one of two preset values are loaded into the offset registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag select (FS1, FS0) inputs during a LOW-to-HIGH transition on the RST input (See Table 1). PRESET VALUES If the preset value of 8 or 64 is chosen by the FS1 and FS0 inputs at the time of a RST LOW-to-HIGH transition according to Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is necessary to begin normal operation, and the IR flag is set HIGH after two LOW-to-HIGH transitions on CLKA. PARALLEL LOAD FROM PORT A To program the X and Y registers from port A, the device is reset with FS0 and FS1 LOW during the LOW-to-HIGH transition of RST. After this reset is complete, the IR flag is set HIGH after two LOW-to-HIGH transitions on CLKA. The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset register of the IDT723631, IDT723641, and IDT723651 uses port-A inputs (A8-A0), (A9-A0), and (A10-A0), respectively. The highest number input is used as the most significant bit of the binary number in each case. Each register value can be programmed from 1 to 508 (IDT723631), 1 to 1020 (IDT723641), and 1 to 2044 (IDT723651). After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM. SERIAL LOAD To program the X and Y registers serially, the device is reset with FS0/SD and FS1/SEN HIGH during the LOW-toHIGH transition of RST. After this reset is complete, the X and
Y register values are loaded bitwise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW. Eighteen-, 20-, or 22-bit writes are needed to complete the programming for the IDT723631, IDT723641, or IDT723651, respectively. The first-bit write stores the most significant bit of the Y register, and the last-bit write stores the least significant bit of the X register. Each register value can be programmed from 1 to 508 (IDT723631), 1 to 1020 (IDT723641), or 1 to 2044 (IDT723651). When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains LOW until all register bits are written. The IR flag is set HIGH by the LOW-toHIGH transition of CLKA after the last bit is loaded to allow normal FIFO operation. FIFO WRITE/READ OPERATION The state of the port-A data (A0-A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA and the port-A mailbox select (MBA) are LOW, W/RA, the port-A enable (ENA), and the input-ready (IR) flag are HIGH (see Table 2). Writes to the FIFO are independent of any concurrent FIFO read. The port-B control signals are identical to those of port-A with the exception that the port-B write/read select (W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0-B35) outputs is controlled by the portB chip select (CSB) and the port-B write/read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH. Data is read from the FIFO to its output register on a LOWto-HIGH transition of CLKB when CSB and the port-B mailbox select (MBB) are LOW, W/RB, the port-B enable (ENB), and the output-ready (OR) flag are HIGH (see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes. The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-
FS1 H H L L
FS0 H L H L
RST

X and Y Registers (1) Serial Load 64 8 Parallel Load From Port A
3023 tbl 08
NOTE: 1. X register holds the offset for AE; Y register holds the offset for AF. Table 1. Flag Programming
9
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port chip select and write/read select may change states during the setup- and hold time window of the cycle. When the output-ready (OR) flag is LOW, the next data word is sent to the FIFO output register automatically by the CLKB LOW-to-HIGH transition that sets the output-ready flag HIGH. When OR is HIGH, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB), write/read select (W/RB), enable (ENB), and mailbox select (MBB). SYNCHRONIZED FIFO FLAGS Each IDT723631/723641/723651 FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the flags' reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows the relationship of each flag to the number of words stored in memory. OUTPUT-READY FLAG (OR) The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). When the outputready flag is HIGH, new data is present in the FIFO output
register. When the output-ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB. Therefore, an outputready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three CLKB cycles have not elapsed since the time the word was written. The outputready flag of the FIFO remains LOW until the third LOW-toHIGH transition of CLKB occurs, simultaneously forcing the output-ready flag HIGH and shifting the word to the FIFO output register. A LOW-to-HIGH transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent CLKB cycle may be the first synchronization cycle (see Figure 6). INPUT READY FLAG (IR) The input ready flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). When the input-
CSA
H L L L L L L L
W/RA R X H H H L L L L
ENA X L H H L H L H
MBA X X L H L L H H
CLKA X X X X
A0-A35 Outputs In High-Impedance State In High-Impedance State In High-Impedance State In High-Impedance State Active, Mail2 Register Active, Mail2 Register Active, Mail2 Register Active, Mail2 Register
Port Functions None None FIFO Write Mail1 Write None None None Mail2 Read (Set MBF2 HIGH)
3023 tbl 09
Table 2. Port-A Enable Function Table
CSB
H L L L L L L L
W/RB
X L L L H H H H
ENB X L H H L H L H
MBB X X L H L L H H
CLKB X X X X
B0-A35 Outputs In High-Impedance State In High-Impedance State In High-Impedance State In High-Impedance State Active, FIFO Output Register Active, FIFO Output Register Active, Mail1 Register Active, Mail1 Register
Port Functions None None None Mail2 Write None FIFO read None Mail1 Read (Set MBF1 HIGH)
3023 tbl 10
Table 3. Port-B Enable Function Table
10
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ready flag is HIGH, a memory location is free in the SRAM to write new data. No memory locations are free when the inputready flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an input-ready flag monitors a write-pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of three cycles of CLKA. Therefore, an input-ready flag is LOW if less than two cycles of CLKA have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on CLKA after the read sets the input-ready flag HIGH, and data can be written in the following cycle. A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent CLKA cycle may be the first synchronization cycle (see Figure 7). ALMOST-EMPTY FLAG (AE AE) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array (CLKB). The state machine that controls an almost-empty flag monitors a writepointer and read-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset,programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset programming above). The almost-empty flag is LOW when the FIFO contains X or less words and is HIGH when the FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of CLKB are required after a FIFO write for the almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X+1) or more words remains LOW if two cycles of CLKB have not elapsed since the write that filled the memory to the (X+1)
level. An almost-empty flag is set HIGH by the second LOWto-HIGH transition of CLKB after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of CLKB begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent CLKB cycle may be the first synchronization cycle (see Figure 8). ALMOST-FULL FLAG (AF AF) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The almost-full flag is LOW when the number of words in the FIFO is greater than or equal to (512-Y), (1024-Y), OR (2048-Y) for the IDT723631, IDT723641, or IDT723651, respectively. The almost-full flag is HIGH when the number of words in the FIFO is less than or equal to [512-(Y+1)], [1024-(Y+1)], or [2048-(Y+1)] for the IDT723631, IDT723641, or IDT723651, respectively. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of CLKA are required after a FIFO read for its almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [512/1024/ 2048-(Y+1)] or less words remains LOW if two cycles of CLKA have not elapsed since the read that reduced the number of words in memory to [512/1024/2048-(Y+1)]. An almost-full flag is set HIGH by the second LOW-to-HIGH transition of CLKA after the FIFO read that reduces the number of words in memory to [512/1024/2048-(Y+1)]. A LOW-to-HIGH transition of CLKA begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [512/1024/2048-(Y+1)]. Otherwise, the subsequent CLKA cycle may be the first synchronization cycle (see Figure 9).
Number of Words in the FIFO(1,2) IDT723631 0 1 to X (X+1) to [512-(Y+1)] (512-Y) to 511 512 IDT723641 0 1 to X (X+1) to [1024-(Y+1)] (1024-Y) to 1023 1024 IDT723651 0 1 to X (X+1) to [2048-(Y+1)] (2048-Y) to 2047 2048
Synchronized to CLKB OR L H H H H
Synchronized to CLKA
AE
L L H H H
AF
H H H L L
IR H H H H L
3023 tbl 11
NOTES: 1. X is the almost-empty offset for AE. Y is the almost-full offset for AF. 2. When a word is present in the FIFO output register, its previous memory location is free. Table 4. FIFO Flag Operation
11
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
SYNCHRONOUS RETRANSMIT The synchronous retransmit feature of the IDT723631/ 723641/723651 allows FIFO data to be read repeatedly starting at a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode at any time and allow normal device operation. The FIFO is put in retransmit mode by a LOW-to-HIGH transition on CLKB when the retransmit mode (RTM) input is HIGH and OR is HIGH. The rising CLKB edge marks the data present in the FIFO output register as the first retransmit data. The FIFO remains in retransmit mode until a LOW-to-HIGH transition occurs while RTM is LOW. When two or more reads have been done past the initial retransmit word, a retransmit is initiated by a LOW-to-HIGH transition on CLKB when the read-from-mark (RFM) input is HIGH. This rising CLKB edge shifts the first retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can be done endlessly while the FIFO is in retransmit mode. RFM must be LOW during the CLKB rising edge that takes the FIFO out of retransmit mode. When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE flags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode and does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set LOW by the write that stores (512 - Y), (1024 - Y), or (2048 Y) words after the first retransmit word for the IDT723631, IDT723641, or IDT723651, respectively. The IR flag is set LOW by the 512th, 1024th, or 2048th write after the first retransmit word for the IDT723631, IDT723641, or IDT723651, respectively. When the FIFO is in retransmit mode and RFM is HIGH, a rising CLKB edge loads the current read pointer with the shadow read-pointer value and the OR flag reflects the new
level of fill immediately. If the retransmit changes the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are needed to switch AE high (see Figure 11).The rising CLKB edge that takes the FIFO out of retransmit mode shifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the change of read pointer used by IR and AF should cause one or both flags to transmit HIGH, at least two CLKA synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tSKEW1 or greater after the rising CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first synchronizing cycle of AF if it occurs at time tSKEW2 or greater after the rising CLKB edge (see Figure 14). MAILBOX REGISTERS Two 36-bit bypass registers are on the IDT723631/723641/ 723651 to pass command and control information between port A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA with MBA HIGH. A LOWto-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB HIGH. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while its mail flag is LOW. When the port-B data (B0-B35) outputs are active, the data on the bus comes from the FIFO output register when the port-B mailbox select (MBB) input is LOW and from the mail1 register when MBB is HIGH. Mail2 data is always present on the port-A data (A0-A35) outputs when they are active. The mail1 register flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-B read is selected by CSB, W/ RB, and ENB with MBB HIGH. The mail2 register flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register.
12
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
CLKA tRSTH CLKB tRSTS tFSS tFSH
RST
FS1,FS0 tPIR IR tPOR OR 0,1 tPIR
AE AF MBF1, MBF2
tRSF
tRSF tRSF
3023 drw 04
Figure 1. FIFO Reset Loading X and Y with a Preset Value of Eight
CLKA
4
RST
tFSS FS1,FS0 tPIR IR tENS1 tENH1 tFSH
ENA tDS A0 - A35 tDH
AF Offset
(Y)
AE Offset
(X)
First Word Stored in FIFO
3023 drw 05
NOTE: 1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values from Port A
13
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
CLKA
4
RST
tPIR IR tFSS FS1/SEN tFSS FS0/SD tFSH tSDS tSDH tSDS tSDH tSPH tSENS tSENH tSENS tSENH
AF Offset
(Y) MSB
AE Offset
(X) LSB
3023 drw 06
NOTE: 1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH. Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially
tCLK tCLKH CLKA IR HIGH tCLKL
tENS2 tENS2
tENH2 tENH2
CSA
W/RA
tENS2 MBA tENS1 ENA tDS A0 - A35 W1
tENH2
tENH1 tDH
tENS1
tENH1
tENS1
tENH1
W2
No Operation
3023 drw 07
tCLK tCLKH CLKB OR HIGH tCLKL
Figure 4. FIFO Write-Cycle Timing
CSB W/RB
MBB tENS1 ENB tMDV B0 - B35 tEN W1 W2
Figure 5. FIFO Read-Cycle Timing 14
tENH1
tENS1
tENH1 tENS1 tA W3
tENH1 No Operation tDIS
tA
3023 drw 08
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
tCLKH CLKA
tCLK tCLKL
CSA
WRA MBA
LOW HIGH tENS2 tENS1 tENH2 tENH1
ENA IR A0 - A35 HIGH tDS W1 tSKEW1 CLKB OR
(1)
tDH
tCLKH 1
tCLK tCLKL 2 3 tPOR tPOR
Old Data in FIFO1 Output Register LOW HIGH LOW tENS1 tENH1
CSB W/RB
MBB ENB
tA B0 -B35 Old Data in FIFO Output Register W1
3023 drw 09
NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and the first word load to the output register may occur one CLKB cycle later than shown.
Figure 6. OR Flag Timing and First Data Word Fallthrough when the FIFO is Empty
15
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB tCLKL
CSB W/RB
MBB ENB
LOW HIGH LOW tENS1 tENH1
OR B0 -B35
HIGH tA
Previous Word in FIFO Output Register Next Word From FIFO
(1)
tSKEW1 CLKA IR FIFO Full LOW HIGH
tCLK tCLKH 1 tCLKL 2 tPIR tPIR
CSA
WRA MBA
tENS2 tENS1
tENH2 tENH1 tDH Write
3023 drw 10
ENA tDS A0 - A35
NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown. Figure 7. IR Flag Timing and First Available Write when the FIFO is Full
CLKA tENS1 ENA tSKEW2 CLKB
(1)
tENH1
1
2 tPAE tPAE
(X+1) Words in FIFO
AE
ENB
X Word in FIFO
tENS1
tENH1
3023 drw 11
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown. 2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Figure 8. Timing for AE when FIFO is Almost Empty
16
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
tSKEW2 CLKA tENS1 ENA tPAF tENH1
(1)
1
2
tPAF
(Depth
(2)
AF
CLKB
[Depth
(2) -(Y+1)]
Words in FIFO
-Y) Words in FIFO
tENS1 ENB
tENH1
3023 drw 12
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown. 2. Depth is 512 for the IDT723631, 1024 for the IDT723641, and 2048 for the IDT723651. 3. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Figure 9. Timing for AF when FIFO is Almost Full
CLKB tENS1 ENB tRMS RTM
tENH1 tRMS tRMS tRMH tRMH
tRMH
RFM OR B0-B35 HIGH tA W0 Initiate Retransmit Mode with W0 as First Word W1 tA tA W2 Retransmit from Selected Position tA W0 End Retransmit Mode W1
3023 drw 13
NOTE: 1. CSB = LOW, W/RB = HIGH, MBB = LOW. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit. Other enables are shown only to relate retransmit operations to the FIFO output register. Figure 10. Retransmit Timing Showing Minimum Retransmit Length
CLKB
1 HIGH tRMS tRMH
2
RTM
RFM
tPAE
AE
X or fewer words from Empty
(X+1) or more words from Empty
3023 drw 14
NOTE: 1. X is the value loaded in the almost empty flag offset register. Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X.
17
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
(1)
COMMERCIAL TEMPERATURE RANGE
tSKEW1 CLKA IR CLKB tRMS RTM tRMH
FIFO Filled to First Restransmit Word
1
2 tPIR
One or More Write Locations Available
3023 drw 15
NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 12. IR Timing from the End of Retransmit Mode when One or More Write Locations are Available
tSKEW2 CLKA
(1)
1
(Depth (2) -Y) or More Words Past First Restransmit Word
2
tPAE
(Y+1) or More Write Locations Available
AF
CLKB
tRMS RTM
tRMH
3023 drw 16
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown. 2. Depth is 512 for the IDT723631, 1024 for the IDT723641, and 2048 for the IDT723651. 3. Y is the value loaded in the almost-full flag offset register. Figure 13. AF Timing from the End of Retransmit Mode when (Y+1) or More Write Locations are Available
18
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
CLKA tENS2 tENH2
CSA
W/RA MBA ENA A0 - A35 tDS W1 tDH
CLKB
MBF1 CSB W/RB
MBB
tPMF
tPMF
tENS1 ENB tEN B0 - B35 FIFO Output Register tMDV tPMR
tENH1
tDIS W1 (Remains valid in Mail1 Register after read)
3023 drw 17
Figure 14. Timing for Mail1 Register and MBF1 Flag
19
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
CLKB
tENS2
tENH2
CSB W/RB
MBB ENB tDS W1 tDH
B0 - B35
CLKA
MBF2 CSA
W/RA MBA
tPMF
tPMF
tENS1 ENA tEN A0 - A35 tPMR
tENH1
tDIS W1 (Remains valid in Mail2 Register after read)
3023 drw 18
Figure 15. Timing for Mail2 Register and MBF2 Flag
20
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 250 fdata = 1/2 fs TA = 25C C L = 0pF 200 V CC = 5.0 V V CC = 5.5 V
150 V CC = 4.5 V
- Supply Current - mA I CC(f)
100
50
0 0 10 20 30 40 50 60 70
3023 drw 19
fs - Clock Frequency - MHz
Figure 16
CALCULATING POWER DISSIPATION The ICC(f) current for the graph in Figure 16 was taken while simultaneously reading and writing the FIFO on the IDT723641 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT723631/723641/723651 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. With ICC(f) taken from FIgure 16, the maximum power dissipation (PT) of the IDT723631/723641/723651 may be calculated by: PT = VCC x [ICC(f) + (N x ICC x dc)] + (CL x VCC2 x fO) where: N = ICC = dc = CL = fO = number of inputs driven by TTL levels increase in power supply current for each input at a TTL HIGH level duty cycle of inputs at a TTL HIGH level of 3.4 output capacitance load switching frequency of an output
When no reads or writes are occurring on the IDT723631/723641/723651, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated by: PT = VCC x fS x 0.209 mA/MHz
21
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k From Output Under Test 680 30 pF
(1)
3V Timing Input tS Data, Enable Input 1.5 V 1.5 V GND th 3V 1.5 V GND Low-Level Input 1.5 V High-Level Input 1.5 V tW 1.5 V
3V GND 3V 1.5 V GND
VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS PULSE DURATIONS
Output Enable tPLZ Low-Level Output
3V 1.5 V 1.5 V tPZL 1.5 V tPZH 1.5 V VOL VOH In-Phase Output GND 3 V Input 3V 1.5 V tPD 1.5 V 1.5 V GND tPD VOH 1.5 V VOL
High-Level Output
tPHZ
OV
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
3023 drw 20
NOTE: 1. Includes probe and jig capacitance Figure 17. Load Circuit and Voltage Waveforms
22
IDT723631/723641/723651 CMOS SyncFIFOTM 512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range
BLANK
Commercial (0C to +70C)
PF PQF 15 20 30
Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) Commercial Only Clock Cycle Time (tCLK) Speed in Nanoseconds
L
Low Power
723631 512 x 36 Synchronous FIFO 723641 1024 x 36 Synchronous FIFO 723651 2048 x 36 Synchronous FIFO
3023 drw 21
23

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